The present invention relates generally to semiconductors. More particularly, the invention relates to electrical interconnects, masks for making such interconnects, and semiconductor devices incorporating such interconnects.
In manufacturing semiconductor devices, various components are formed on a silicon substrate and electrically connected together with interconnects. For instance, after a component such as a transistor has been fabricated, interconnects are used to connect it with another component. This connection process is commonly known as “metallization”, which may incorporate various photolighographic and deposition techniques.
In general, interconnects are solid metal pieces that span across a dielectric layer. In addition, interconnects may be solid metal vias that span between dielectric layers. In forming some interconnects, planarization is typically performed on both the dielectric layers and the interconnects. Planarization may include using a chemical-mechanical polishing (CMP) process. In some cases, especially when wider interconnects are used for power buses/rails, the interconnects are more susceptible to higher degrees of dishing effects during planarization. That is, surface portions of the interconnects may end up with substantially different heights relative to the surfaces of their surrounding dielectric layers, thereby resulting with different thicknesses and potentially increased resistances. Such non-uniformity of interconnects within the semiconductor often leads to integration and manufacturing problems, which in turn can lead to various performance problems (e.g., increased time delays, less robust connectivity, etc.).
Accordingly, it would be beneficial to be able to form interconnects that can be integrated into semiconductor devices so that their performances are improved.